Hi Hirokuni,
"Hold delay" is the time you need to drive CSn low in order for CC85xx to interpret this as a button type Hold ("H" in IO Mapping panel).
"Minimum idle time" is the minimum time between two concequtive Holds in order for the second Hold to be registered and executed.
In your figure 1 it looks that you are driving the CSn low for 1.6 seconds, then driving it high for 200ms, then low again for 1.6 seconds. If it was OFF initially it will go ON then OFF again since you are holding and releasing according to the timing you have set up.
In your figure 2 it seems that you are driving CSn low for 1 second, then driving it high for 20 ms, then low again for 1 second. If it was OFF initially it should go ON then OFF again since you are holding and releasing according to the timing you have set up.
Have I understood your figure and your problem correctly?
It could be that 20 ms is too fast because the chip is still in the process of waking up... What if you try to increase the "Minimum idle time". How large must "Minimum idle time" be in order to achieve expected behaviour?
Best regards
Kristoffer
-Kristoffer