Forum Post: RE: CC113L and CC115L recieve problem

Hi,

Im using fixed packet lenght mode and PKTLEN=0x01 here is configuration;

TX;

CS=0;
    _delay(60);
    spi_transfer(0x36);

    spi_transfer(IOCFG2);    spi_transfer(0x2e);
    spi_transfer(IOCFG1);    spi_transfer(0x2e);
    spi_transfer(IOCFG0);    spi_transfer(0x06);
    spi_transfer(FIFOTHR);   spi_transfer(0x00);
    spi_transfer(SYNC1);     spi_transfer(0xd3);
    spi_transfer(SYNC0);     spi_transfer(0x91);
    spi_transfer(PKTLEN);    spi_transfer(0x01);
    spi_transfer(PKTCTRL0);  spi_transfer(0x04);
    spi_transfer(CHANNR);    spi_transfer(0x00);
    spi_transfer(FSCTRL0);   spi_transfer(0x00);
    spi_transfer(FREQ2);     spi_transfer(0x21);
    spi_transfer(FREQ1);     spi_transfer(0x62);
    spi_transfer(FREQ0);     spi_transfer(0x76);
    spi_transfer(MDMCFG4);   spi_transfer(0xf5);
    spi_transfer(MDMCFG3);   spi_transfer(0x83);
    spi_transfer(MDMCFG2);   spi_transfer(0x43);
    spi_transfer(MDMCFG1);   spi_transfer(0x22);
    spi_transfer(MDMCFG0);   spi_transfer(0xf8);
    spi_transfer(DEVIATN);   spi_transfer(0x15);
    spi_transfer(MCSM1);     spi_transfer(0x30);
    spi_transfer(MCSM0);     spi_transfer(0x28);
    spi_transfer(0x20);      spi_transfer(0xfb);
    spi_transfer(FREND0);    spi_transfer(0x10);
    spi_transfer(FSCAL3);    spi_transfer(0xe9);
    spi_transfer(FSCAL2);    spi_transfer(0x2a);
    spi_transfer(FSCAL1);    spi_transfer(0x00);
    spi_transfer(FSCAL0);    spi_transfer(0x1f);
    spi_transfer(PATABLE);   spi_transfer(0x5C);
    CS=1;

RX;

  SPIWriteReg(IOCFG2,   0x06); // GDO2 output pin config.
    SPIWriteReg(IOCFG0,   0x06); // GDO0 output pin config.
    SPIWriteReg(PKTLEN,   0x01); // Packet length.
    SPIWriteReg(PKTCTRL1, 0x04); // Packet automation control.
    SPIWriteReg(PKTCTRL0, 0x04); // Packet automation control.
    SPIWriteReg(ADDR,     0x00); // Device address.
    SPIWriteReg(CHANNR,   0x00); // Channel number.
    SPIWriteReg(FSCTRL1,  0x06); // Freq synthesizer control.
    SPIWriteReg(FSCTRL0,  0x01); // Freq synthesizer control.
    SPIWriteReg(FREQ2,    0x21); // Freq control word, high byte
    SPIWriteReg(FREQ1,    0x62); // Freq control word, mid byte.
    SPIWriteReg(FREQ0,    0x76); // Freq control word, low byte.
    SPIWriteReg(MDMCFG4,  0xF5); // Modem configuration.
    SPIWriteReg(MDMCFG3,  0x83); // Modem configuration.
    SPIWriteReg(MDMCFG2,  0x43); // Modem configuration.
    SPIWriteReg(MDMCFG1,  0x22); // Modem configuration.
    SPIWriteReg(MDMCFG0,  0xF8); // Modem configuration.
    SPIWriteReg(DEVIATN,  0x00); // Modem dev (when FSK mod en)
    SPIWriteReg(MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    SPIWriteReg(MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    SPIWriteReg(FOCCFG,   0x1D); // Freq Offset Compens. Config
    SPIWriteReg(BSCFG,    0x1C); //  Bit synchronization config.
    SPIWriteReg(AGCCTRL2, 0xC7); // AGC control.
    SPIWriteReg(AGCCTRL1, 0x00); // AGC control.
    SPIWriteReg(AGCCTRL0, 0xB2); // AGC control.
    SPIWriteReg(FREND1,   0xB6); // Front end RX configuration.
    SPIWriteReg(FREND0,   0x10); // Front end RX configuration.
    SPIWriteReg(FSCAL3,   0xE9); // Frequency synthesizer cal.
    SPIWriteReg(FSCAL2,   0x2A); // Frequency synthesizer cal.
    SPIWriteReg(FSCAL1,   0x00); // Frequency synthesizer cal.
    SPIWriteReg(FSCAL0,   0x1f); // Frequency synthesizer cal.
    SPIWriteReg(FSTEST,   0x59); // Frequency synthesizer cal.
    SPIWriteReg(TEST2,    0x88); // Various test settings.
    SPIWriteReg(TEST1,    0x31); // Various test settings.
    SPIWriteReg(TEST0,    0x0B); // Various test settings.
    SPIWriteReg(SYNC1,    0xd3);
    SPIWriteReg(SYNC0,    0x91);

and when Im reading Im waiting GDO2. when GDO2 is high Im starting read after some little delay. Im sending 1 byte and Im trying read 1 byte.