MaciejKucia,
Thank you for your post!
Yes, I confirmed the button interrupt to verify the interrupt and de-bounce function are doing okay.
Well, if I combine the small functions, the reset function is like:
void chip_reset(void)
{
bit_num = 0x00;
temp_byte = 0x00;
// Initialize Clock (32 Mhz Xtal), global interrupt (EA=1), I/O ports, SPI mode and reciever
clockSetMainSrc(CLOCK_SRC_XOSC);
while (CLKCONSTA != 0x80);
halBoardInit(); //This is the same as the halBoardInit() used in PERTest
EA = 1; //enables interrupts (global)
P0DIR &= ~BIT1; // P0.1: Button 1 (input)
P0INP &= ~BIT1; // Select input type as pull up/pull down.
PPULL |= BIT1; // Pull down
RFERRIE = 1;
while (RFST != 0);
//Disable Radio
LLECTRL = 0x00; //LLE held in Reset
//from smart RF register export
memset((void*)RFCORE_RAM_PAGE, 0, RFCORE_RAM_PAGE_SZ); //defined in ioCC2544.h Page=PXREG( 0x6000 ) Size=128
/* RF settings SoC: CC2543 */ //Receiver mode
PRF_CHAN = 0x29; //
PRF_TASK_CONF = 0x01; // configuration of task control
PRF_PKT_CONF = 0x06; // packet configuration
PRF_CRC_LEN = 0x02; // crc length.
PRF_CRC_INIT_2 = 0xFF; // initialization value for crc.
PRF_CRC_INIT_3 = 0xFF; // initialization value for crc.
PRF_ADDR_ENTRY_0_0 = 0x01; // address entry 0, index 0. basic mode: conf. see user guide for details on auto mode.
PRF_ADDR_ENTRY_0_1 = 0x40; // address entry 0, index 1. basic mode: rxlength
PRF_RADIO_CONF = 0x90; // configure radio hardware.
FRMCTRL0 = 0x41; //
FREQCTRL = 0x2A; //
TXPOWER = 0xE5; // output power control
LLESTAT = 0x04; // lle status
MDMCTRL0 = 0x06; // modem configuration
MDMCTRL1 = 0x48; // modem configuration
MDMCTRL2 = 0x4C; // modem configuration
MDMCTRL3 = 0x63; // modem configuration
SW0 = 0x29; // primary sync word byte 0
SW1 = 0x41; // primary sync word byte 1
SW2 = 0x76; // primary sync word byte 2
SW3 = 0x71; // primary sync word byte 3
RXCTRL = 0x29; // receive section tuning
FSCTRL = 0x5A; // frequency synthesizer tuning
ADCTEST0 = 0x66; //
MDMTEST0 = 0x0F; // modem configuration
MDMTEST1 = 0x25; // modem configuration
LLECTRL = 0x01; // lle control
RFRAMCFG = 0x00; // radio ram configuration
BSP_P1 = 0x00; // crc polynomial byte 1
BSP_P2 = 0x21; // crc polynomial byte 2
BSP_P3 = 0x10; // crc polynomial byte 3
BSP_MODE = 0x00; // bit stream processor configuration
while (RFST != 0);
//Enable link layer engine
LLECTRL = 0x01;
RFFCFG |= (BIT5|BIT4); //auto commmit & dealloc FIFO (TX) -- P278
RFFCFG |= (BIT1|BIT0); // auto commit & dealloc RxFIFO - P278
}
Thank you again for your time and consideration.