Hi Kjetil
I Currently use this configuration, but my customer can hear sound delay.
# PIN RESET
p Reset 1 # Release the reset pin
# RESET
w 30 00 00 # Select register page 0
w 30 01 01 # I2C reset
# CLOCK SETTINGS
w 30 12 81 # Power up the NADC divider with value 1
w 30 13 82 # Power up the MADC divider with value 2
w 30 14 80 # Program OSR for ADC to 128
# DIGITAL INTERFACE
w 30 1B 00 # I2S, 16-bit, BCLK and WCLK are inputs
# PROCESSING BLOCK USAGE
w 30 3D 01 # Select ADC processing block PRB_R1
# ANALOG POWER SUPPLY
w 30 00 01 # Select register page 1
w 30 01 08 # Disable internal crude AVDD before powering up the internal AVDD LDO
w 30 02 01 # Enable internal analog LDO, analog blocks powered
w 30 0A 40 # Common mode set to 0.75V
# MICPGA DELAY, REFERENCE CHARGING AND HEADPHONE DE-POP
w 30 47 31 # MICPGA startup delay is 3 ms
w 30 7B 01 # Reference charging time is 40 ms
# AUDIO ROUTING
w 30 34 51 #12-L is routed to Left MICPGA with 10K resistance
w 30 36 51 #12- CML is routed to Left MICPGA via CM1L with 10K resistance
w 30 37 51 #12-R is routed to Right MICPGA with 10K resistance
w 30 39 51 #12- CMR is routed to Right MICPGA via CM1R with 10K resistance
# DC FILTER LEFT CHANNEL
w 30 00 08 # Select register page 8
w 30 18 7F # n0 + n1 * z^-1
w 30 19 FF # H(z) = ----------------------
w 30 1A 00 # 2^23 - d1 * z^-1
w 30 1C 80 #
w 30 1D 01 # The constants are defined as
w 30 1E 00 # n0 = 32767 * 256
w 30 20 7F # n1 = -32767 * 256
w 30 21 FC # d1 = 32768 * 256 * (1- 2^13)
w 30 22 00 # This gives a filter with cutoff at approx. 1 Hz
# DC FILTER RIGHT CHANNEL
w 30 00 09 # Select register page 9
w 30 20 7F # n0 + n1 * z^-1
w 30 21 FF # H(z) = ----------------------
w 30 22 00 # 2^23 - d1 * z^-1
w 30 24 80 #
w 30 25 01 # The constants are defined as
w 30 26 00 # n0 = 32767 * 256
w 30 28 7F # n1 = -32767 * 256
w 30 29 FC # d1 = 32768 * 256 * (1- 2^13)
w 30 2A 00 # This gives a filter with cutoff at approx. 1 Hz