Hi Aoran,
Now that voltage level on SPI clk has been excluded, let's take a step back and see what could be the reason.
I am still concerned about timing, including SPI timing and power-on sequence.
None of the waveforms above hits the 37.5ns maximal high pulse width, as specified in the CC3000 datasheet. But the datasheet also states that 0~16MHz clock frequency is acceptable. I don't feel it is reasonable. For example, my MCU supports SPI clock up to 16MHz, however, it seems there is no way adjust the duty cycle. As a result of 50% duty cycle by default, the only way to reach that 37.5ns is to increase clock speed to 26MHz. But that's overkill for SPI.
Speaking of power-on sequence, do you think the process of MCU initialization after board power up, including setting GPIOs for EN and CS, would affect init of CC3000? From most posts I have seen online, they are debugging the init in firmware, not in CCS, where the init of CC3000 could be executed immediately after power up of the board. As you can see in the screenshot of board power up, the IRQ has already been dropped, indicating the module is ready to receive data. However we didn't write to it until we started to run CCS a long while later. The states of CS and EN were also toggled half way in the middle when their GPIOs were configured, though they returned very quickly while IRQ remained low.
How do you think about it?
Meanwhile I am going to try wiring the SPI to one CC3000 evaluation board from LS Research, and see what happens.
Thanks,
Dawei
