Forum Post: CC2543 dropping packets?

I have two 2543 SmartRF Eval kits running.  Board 1 starts by transmitting packets.  Board 2 starts by waiting for a received packet.  Every 10msec board 1 transmits a new packet.  Each new packet has a different length and the sequence number in my packet increments.  I'm not using the sequence number check in the chip, but I do look at it for my testing in my software.  Board 1 goes into receive mode until either a packet is received and then waits for 10msec to send the next packet, or it times out after 100msec because there was no packet to receive and then sends out the next packet.  Board 2 ideally receives a packet from board 1, changes one of the bytes (so in debugging I know which board was the last board to send from looking at my sniffer) and transmits it back to board 1.  But, they are dropping packets.  Board 1 sends a packet, changes to receive mode.  Board 2 reads the packet and transmits it back to board 1.  Board 1 does not see the packet.  My sniffer sees the packet just fine so I know it transmitted.  I suspect there is something in the turnaround from transmit to receive.  Most of the time it works, occasionally it doesn't.  It doesn't seem to have anything to do with the packet size.  CRC is enabled, but I'm not seeing any CRC errors that I can see.  Basic mode, variable length.  Not using DMA.  When I get the timeout error, RFERRF = 0, RFSTAT = 0x25, RFFSTATUS = 0x66.

    PRF.TASK_CONF.MODE = 1;                        // Basic mode, variable length
//    PRF.TASK_CONF.MODE = 0;                        // Basic mode, Fixed length
    PRF.TASK_CONF.REPEAT = 0;                    // single operation.
    PRF.TASK_CONF.START_CONF = 0;                // Start immediately after command.
    PRF.TASK_CONF.STOP_CONF = 0;                // Don't Stop immediately on timer 2 event 2.
    PRF.FIFO_CONF.AUTOFLUSH_IGN = 0;            // Don't Flush duplicate packets.
    PRF.FIFO_CONF.AUTOFLUSH_CRC = 0;            // Don't flush packets with CRC error.
//    PRF.FIFO_CONF.AUTOFLUSH_CRC = 1;            // Flush packets with CRC error.
    PRF.FIFO_CONF.AUTOFLUSH_EMPTY = 0;            // Flush packets with no payload.
    PRF.FIFO_CONF.RX_STATUS_CONF = 0;            // Do not append status information in FIFO.
    PRF.FIFO_CONF.RX_ADDR_CONF = 0;                // Do not include address byte in Rx FIFO (no config).
//    PRF.FIFO_CONF.RX_ADDR_CONF = 1;                // Include address byte in Rx FIFO (no config).
                                                // add one to the received packet size to read.
    PRF.FIFO_CONF.TX_ADDR_CONF = 0;                // Read address from PRF.ADDR_ENTRY[0].ADDRESS.
//    PRF.PKT_CONF.ADDR_LEN = 0x00;                // no address byte.
    PRF.PKT_CONF.ADDR_LEN = 0x01;                // One address byte - last byte in the 5 byte address.
                                                // For CRC to work, needed to make this 1.  Add 1 to the packet
                                                // length to read out.
//    PRF.CRC_LEN = 0;                            // no CRC.
    PRF.CRC_LEN = CRCLEN;                        // 2 byte CRC.
    PRF.ADDR_ENTRY[0].CONF.ENA0 = 1;            // Enable address entry for primary sync word.
//    PRF.ADDR_ENTRY[0].CONF.ENA0 = 0;            // Disable address entry for primary sync word.
//    PRF.ADDR_ENTRY[0].CONF.TXLEN = 0;            // Insert packet length in header when transmitting.
//    PRF.ADDR_ENTRY[0].RXLENGTH = 121;            // Set length equal to packet length + address byte.
                                                // For fixed length, still needed to add 1 for the CRC calc.
    PRF.ADDR_ENTRY[0].RXLENGTH = 127;            // Set length equal to packet length + address byte.
                                                // For fixed length, still needed to add 1 for the CRC calc.
    PRF.ADDR_ENTRY[0].ADDRESS = 0xE5;            // Address.
    PRF.ADDR_ENTRY[0].CONF.REUSE = 0;            // LLE deallocates packet after it has been acknowledged.


    // Common recommended register settings changes.
    TXPOWER = 0xE5;                // Set default output power: 4dBm.
    FRMCTRL0 = 0x43;            // Amplitude weight in frequency offset compensation (assuming sync word included in CRC and MSB first).
    MDMCTRL1 = 0x48;            // Set correlation threshold.
    MDMCTRL3 = 0x63;            // Set RSSI mode to peak detect after sync.
    ACOMPQS = 0x16;                // Finetune Q phase relative I (i.e. skewness).
    TXFILTCFG = 0x07;            // Set Tx filter bandwidth.
    FSCTRL = 0x5A;                // Prescaler and mixer currents.
    ADCTEST0 = 0x66;            // Reduce ADC gain.


    // Set CRC initialization value.
    PRF.CRC_INIT[0] = 0x00;
    PRF.CRC_INIT[1] = 0x00;
    PRF.CRC_INIT[2] = 0xFF;
    PRF.CRC_INIT[3] = 0xFF;

    // Set BSP polynomial to CRC-16-CCITT (x^16 + x^12 + x^5 + 1).
    BSP_P0 = 0x00;
    BSP_P1 = 0x00;
    BSP_P2 = 0x21;
    BSP_P3 = 0x10;

    // Seed pseudo-random generator.
    RNDL = 0x00;
    RNDL = 0xFF;

    // Program sync word.
    SW0 = 0x29;
    SW1 = 0x41;
    SW2 = 0x76;
    SW3 = 0x71;

    // Disable whiteners.
    BSP_MODE = 0x00;
    // 32 bits long SW.
    SW_CONF = 0x00;