Regarding the race condition, could you describe the nature of the fix? I'm assuming the race is when the host is writing to CC3000 and it simultaneously receives radio RX data -- is this correct? To confirm, the issue appears as an early IRQ assertion (after CS asserted) which causes an early write (before CC3000 ready)? [since the IRQ changed meanings during the write operation and became "host attention", not "SPI ready"?]
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