Hi Eirik,
Thanks for your help. Our application requires reading data in from SPI from one source, writing out through SPI to another destination, and then reading from SPI and transmitting that data through the radio. I want to do this without impacting the throughput rate of the radio (which I understand with overhead and turnaround will be less than 2Mbs). So in order to accomplish all of this and not starve the TXFIFO, the DMA must fill the TXFIFO at four times the emptying rate. Can you tell me what the ideal DMA transfer rate for DATA to SFR is if nothing else is happening on chip (or asked differently, how many clock cycles does a DMA transfer require)?
thanks again,
Mitch