Hello,
5535's Spi works such that you can only add 0, 1, .. 4 bits delay between CS assertion and first CLK edge. However, with CC3000, one has to assert CS and wait until IRQ goes low before starting sending data.
So here is my question, can I assert CS, write a busy byte (0x00), then wait until CC3000 modules asserts IRQ and process normaly from there? Or does the line have to remain completely quiet for this laps of time?(It is the only wait I can assert CS line with 5535)
Please answer! It is quite important for me to know before I have to go through a painfull hardware modification to use GPIO.
Regards,
Jean