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Forum Post: RE: CC2530 ADC offset and gain compensation

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thank you for your answer..

I do 20 measure every sampling so I think I hope to reduce the effect of INL.

In input I have a regulated supply voltage and I do a test measure from 0 to 2500mV, I use an Agilent 6dgt multimeter to verify the value. I take the measure with reference P0_7 where I have a TI REF3325.

I do single ended measure, so with 12bit I have 11bit  ( 0 to 2047), correct? If I consider the 0 I have 2048 levels.

I post the measure I have done:

Vinput ADC register ADC register ( expected )
4,8 0,0 3,9
15,5 6,0 12,7
21,5 11,0 17,6
244,0 194,0 199,9
311,0 253,0 254,8
399,0 325,0 326,9
514,0 421,0 421,1
601,0 494,0 492,3
722,0 594,0 591,5
819,0 674,0 670,9
912,0 752,0 747,1
1030,0 850,0 843,8
1121,0 925,0 918,3
1229,0 1015,0 1006,8
1319,0 1089,0 1080,5
1662,0 1373,0 1361,5
1700,0 1405,0 1392,6
1706,0 1410,0 1397,6
1805,0 1492,0 1478,7
1928,0 1594,0 1579,4
2129,0 1761,0 1744,1
2226,0 1841,0 1823,5
2350,0 1944,0 1925,1
2421,0 2003,0 1983,3
2470,0 2043,0 2023,4
2475,0 2047,0 2027,5

The expected value is ADCvalue*2500/2048.

If you take a look to the results, we have an offset that variable from about 4mV to 20mV.

With a software compensation from these values I have obtain better results, but I would be sure this is a "normal" behavior.

thank you

Regards,

Emanuele


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