Hi Siri,
Yes, I'm using the variable packet length, but every packet I send/receive is about 19-20 bytes size, and PKTLEN is 0xFF. And for all packets received I verify the CRC to see if it is ok. Here is the reception of a packet:
uint8_t RADIO_Receive_Packet (uint8_t *packet, uint8_t *size) {
uint8_t receivedPktLenght, status[2], ok;
ok = 0;
if ((RADIO_Read_Status(CCxxx0_RXBYTES) & 0x7F)) { // if there is bytes in fifo
receivedPktLenght = RADIO_Read_Reg(CCxxx0_RXFIFO);
if (receivedPktLenght <= *size) {
RADIO_Read_Burst(CCxxx0_RXFIFO, packet, receivedPktLenght);
*size = receivedPktLenght;
RADIO_Read_Burst(CCxxx0_RXFIFO, status, 2);
ok = (status[1] & 0x80); // CRC ok is the MSB of status[1]
RADIO_Strobe(CCxxx0_SIDLE);
RADIO_Strobe(CCxxx0_SFRX);
}
else {
*size = receivedPktLenght;
RADIO_Strobe(CCxxx0_SIDLE);
RADIO_Strobe(CCxxx0_SFRX);
ok = 0;
}
}
return ok;
}
this is the configuration of the radios, sorry for not writing them earlier:
static settingsCC1101 RADIO_915 = {
0x0C, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x23, // FREQ2 Frequency control word, high byte.
0x31, // FREQ1 Frequency control word, middle byte.
0x3B, // FREQ0 Frequency control word, low byte.
0x2D, // MDMCFG4 Modem configuration.
0x3B, // MDMCFG3 Modem configuration.
0x13, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x62, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end TX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB0, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x07, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF® Studio User Manual for detailed pseudo register explanation.
0x04, // PKTCTRL1 Packet automation control.
0x05, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
The register MCSM2 is woking as I said in the last post, is there a problem switching the value of it like I am doing?
Thank you Siri,
Bruno.