Hi Tim, This is behavior is expected. The reason is that when using the SPI_POl0_PHA0 mode, the SPI master hardware requires the mater to toggle the FSS (chip select) pin between each transferred word. In any other frame format, you would be OK as this example implements a 3-wire SPI per default. If you want to use the SPI_POL0_PHA0 frame format, you will need to also assign and connect a chip select pin for the SPI driver in the board file.
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