[quote user="David Paulsen"]Thanks so much for your suggestions! I think I found the problem. The FPGA has a PLL that generates its clock frequency, and it seems to have a startup problem. When it fails, the SPI frequency is almost 3 Mbps instead of 2 Mbps. With that fixed, it seems to work much more reliably now.[/quote]
I didn't see this follow-up when I posted the previous reply (I had started writing it some hours ago). I am glad you found the issue!