I just did another logic capture and I think I have more specific information to share. I start off by initializing all of my registers. For the first two registers that I transmit to, I get back a status bytes of 0xFF, these are returned at the same time, so should each refer to the previous transmission to line them up? The remaining registers all transmit properly returning a status byte of 0x0F for each one. Once I get into the extended registers, each of the three bytes receives a status byte pattern of 0x0F 0x00 0x0F.
Then I begin a FIFO burst access of 30 bytes. Each byte receives a status byte returned of 0x0F. CSn is brought back high, then I drop it low again and command strobe 0x35 to flush the FIFO. When I send the flush command, the byte that is returned at the exact same time is 0x0F (again, is that for the command at the same time or the previous command?). Then when I go to begin another 30 byte transmission, every single status byte that I receive is 0x5F for the second packet. Then when it goes to send another 30 packets, the received status bytes are all 0x2F. Then the status bytes start decrementing and are all different.
Any idea where the error is happening and how to debug it?
Thanks!