Note that the CC1120 ref design uses the following PCB stack-up (from the readme.txt file in the zip):
PCB DESCRIPTION:4 LAYER PCB 1.24 MM nominal
Copper 1 35 um
Dielectric 1-2 0.4 mm (e.g. 2x Prepreg 7628 AT05 47% Resin)
Copper 2 35 um
Dielectric 2-3 0.3 mm (2 x 2157 49% Resin)
Copper 3 35 um
Dielectric 3-4 0.4 mm (e.g. 2x Prepreg 7628 AT05 47% Resin)
Copper 4 35 um
Hence you have not followed the reference design. In your design the parasitics are higher than in the ref design and therefore the PA load is different something that can explain higher current consumption (the PA power consumption is dependent of where in the smith chart the load is). We have seen similar effects on a different customer case. I would recommend to respin the board with the same stack up as in the ref design.